Field of the Invention
This invention relates generally to the field of computer processors. More particularly, the invention relates to systems and methods for pausing processor trace for efficient analysis.
Description of the Related Art
An instruction set, or instruction set architecture (ISA), is the part of the computer architecture related to programming, including the native data types, instructions, register architecture, addressing modes, memory architecture, interrupt and exception handling, and external input and output (I/O). It should be noted that the term “instruction” generally refers herein to macro-instructions—that is instructions that are provided to the processor for execution—as opposed to micro-instructions or micro-ops—that is the result of a processor's decoder decoding macro-instructions. The micro-instructions or micro-ops can be configured to instruct an execution unit on the processor to perform operations to implement the logic associated with the macro-instruction.
The ISA is distinguished from the microarchitecture, which is the set of processor design techniques used to implement the instruction set. Processors with different microarchitectures can share a common instruction set. For example, Intel® Pentium 4 processors, Intel® Core™ processors, and processors from Advanced Micro Devices, Inc. of Sunnyvale Calif. implement nearly identical versions of the x86 instruction set (with some extensions that have been added with newer versions), but have different internal designs. For example, the same register architecture of the ISA may be implemented in different ways in different microarchitectures using well-known techniques, including dedicated physical registers, one or more dynamically allocated physical registers using a register renaming mechanism (e.g., the use of a Register Alias Table (RAT), a Reorder Buffer (ROB) and a retirement register file). Unless otherwise specified, the phrases register architecture, register file, and register are used herein to refer to that which is visible to the software/programmer and the manner in which instructions specify registers. Where a distinction is required, the adjective “logical,” “architectural,” or “software visible” will be used to indicate registers/files in the register architecture, while different adjectives will be used to designate registers in a given microarchitecture (e.g., physical register, reorder buffer, retirement register, register pool).
Hardware tracing can be used for software debugging, profiling and performance analysis, and malware detection. Processor tracing provides detailed information about software execution, but does so by generating a lot of data. Thus, in the interest of limiting storage requirements and trace processing time, it is desirable to be able to limit tracing only to code of interest.
Because of the potential to expose sensitive details on the execution of privileged software, tracing can only be configured and enabled from within a protected domain (e.g., in Intel architectures, from within ring 0). However, this can lead to costly system calls, as applications in less protected domains are not enabled to modify the processor trace configuration, due to potential security risks.